In integrated circuits, such as Application Specific Integrated Circuits (ASICs) (e.g., graphics processing chips), various circuits or sub-circuits within the integrated circuit are supplied with supply voltages driving or providing power to these circuits. In particular circuits, such as a digital-to-analog converter (DAC) array or multiple bank it is desirable to provide the same power supply voltage to each DAC channel (i.e., each individual digital-to-analog converter circuit in the DAC array). More specifically, in graphics processing integrated circuits, multiple DAC channels are used when driving a monitor or similar display medium. When power supplies to each of the DAC channels are matched, the most accurate color reproduction and acuity is achieved when displaying images on the display medium. Conversely, when the power supply voltages are not closely matched between each of the individual DAC channels, color reproduction and acuity become degraded.
FIG. 1 illustrates an example of a graphics processing integrated circuit 102 including multiple digital-to-analog channels 104 being driven by a display engine 106. The display engine 106, as an example, may receive render image data from a 3-D engine 108 based on data received from an external processor such as a central processing unit [CPU] (not shown). The rendered images are sent by the display engine 106 to a multiple bank of digital-to-analog converters 110, as an example, wherein each DAC channel 104 converts digital data to analog voltages or currents for driving a display medium 112. For example, each of the DAC channels 104 may convert data concerning different colors in a pixel (i.e., RGB). In order to ensure that the colors are most accurately reproduced and acuity is optimal, supply voltages to each of the respective DAC channels 104 should ideally be matched or equal.
Conventional construction of voltage supply traces delivering supply voltages within integrated circuits, however, inherently introduce voltage losses due to IR drop that, in turn, give rise to voltage mismatch between different DAC channels. As an example, FIG. 2 illustrates a conventional voltage supply where a voltage is delivered to an input/output (I/O) pad 200 that is, in turn, delivered from the I/O pad 200 to respective circuits “A” 202 and “B” 204 by a metal trace 206, for example. FIG. 2, in particular, illustrates the physical layout of the voltage supply trace 206 as it is connected to different circuits, such as circuits 202 and 204. FIG. 3 illustrates an equivalent circuit diagram of the physical configuration of FIG. 2. As illustrated, the voltage supply 300, which is shown as a DC voltage supply, delivers power over the trace or bus 206 to the circuits 202 and 204. As current flows through the bus 206, the inherent resistance or impedance of the metal trace, which typically constitutes the bus 206, leads to voltage drops as governed by Ohm's Law. (i.e., V=IR).
Current in the bus flows through a first part of the bus 206 represented by resistor 302 in FIG. 3. This resistance 302 is present in the port of the bus 206 between the I/O pad 200 and a connection node 304 where the bus 206 connects to circuit 202. A voltage supply VDD(A) is present at this node 304, which is the input to circuit 202. As shown in FIG. 3, a second node 306 is illustrated where circuit 204 connects to the bus 206. Additional resistance occurs between nodes 304 and 306 in the metal trace of the bus 206. This resistance is illustrated in FIG. 3 by resistance 308. As current flow through the resistance 308 and as a result an additional voltage drop occurs between nodes 304 and 306, voltage VDD(B) which may be different from VDD(A), is delivered to circuit B 204. In circuits having lower current consumption, the voltage drops due to the bus resistances in 302 and 308 are, for the most part, negligible and do not result in significant voltage mismatch between VDD(A) and VDD(B). However, if circuit 204, draws a high current, the voltage drop across resistor 308, for example, becomes significant and results in a detrimental mismatch between VDD(A) and VDD(B).
In order to cure the problems inherent with a linear metal trace as illustrated in FIGS. 2 and 3, it is known in the art to mitigate the effects of the layout of FIG. 2 by matching the lengths of the metal traces to each of the circuits A and B (202, 204) in order to minimize voltage mismatch. An example of such a configuration is illustrated in FIGS. 4 and 5. FIG. 4, in particular, illustrates the physical layout where voltage is supplied to an I/O pad 400 supplying the circuits A and B (202, 204). The power supply bus 402, which may consist of a metal trace, as an example, is split at a tee region or star-connection 404, with two traces 406 and 408 emanating from the tee region 404 to supply voltage to circuits 202 and 204, respectively. As shown, the trace 406 includes a structural configuration (e.g., a serpentine or u-shaped trace) whereby the length of trace 406 is matched to the length of trace 408.
FIG. 5 illustrates an equivalent circuit diagram of the physical layout of FIG. 4. As shown, a voltage supply 500 supplies voltage to the bus 402, where the common portion prior to the star-connection has an inherent resistance as illustrated by resistor 502. The tee portion 404 of the star connection then splits the bus to supply respective voltages to circuits 202 and 204 via the legs 406 and 408. Each of these traces 406 and 408 have the same length or, more specifically, the same current and resistance product such that the inherent respective voltage (IR) drops through 504 and 506 are equal. Accordingly, when the currents ICCTA and ICCTB are equal, the voltages VDD(A) and VDD(B) are matched. Although the circuits of FIGS. 4 and 5 serve to reduce the mismatch of voltages predominant in the circuits FIGS. 2 and 3, voltage mismatch may still occur, especially when one of the circuits has a higher current draw than the other circuit, resulting in voltage mismatch. This mismatch may further be exacerbated by the problems inherent in manufacturing, such as low tolerances where matching the lengths and current densities of legs 406 and 408 do not yield a perfect matching of resistances 504 and 506. Thus, given uncertainties in processing tolerances of the integrated circuit, there is a limit to which matching of the voltage drop due to IR can be realized. Further, different criterion may further degrade or worsen voltage matching if each of the circuits A and B must have individual power bus connections, which may result in additional compounding voltage mismatch due to bond wire impedances within and board trace impedances to the integrated circuit package.